1. Field of the Invention
This invention relates to a phase control circuit for a digital chrominance signal, for example, for use in a drop-out compensation circuit, a variable speed reproducing circuit and so on.
2. Description of the Prior Art
It is frequently required to control a phase of a video signal in the recording and reproducing thereof, such as in a drop-out compensation circuit and in a hue control circuit.
FIG. 1 shows one example of a drop-out compensation circuit which is used in a reproducing circuit of a VTR (video tape recorder) and which is disclosed in greater detail in U.S. Pat. No. 3,463,874.
Referring to FIG. 1, a reproduced video signal which is supplied to an input terminal 101 is supplied to a switch 102 and to an Y/C separator 103 from which a luminance signal Y and a chrominance signal C are separately derived. The separated luminance and chrominance signals are supplied to 1H (H is the horizontal period) delay lines 104 and 105, respectively. The delayed chrominance signal is supplied to a chroma inverter 110 in which the phase of the subcarrier thereof is inverted and the resulting inverted chrominance signal C' is then combined with the luminance signal Y by an adder 106.
The combined video signal is supplied to one of two fixed contacts of a switch 102, and the other of the fixed contacts is connected to input terminal 101. When a drop-out occurs, the switch 102 is controlled such that the movable contact thereof is disposed in the illustrated position, that is, connected to the output side of the adder 106 to thereby provide at the output of switch 102, a compensation video signal having no drop-out. The reason why the phase-inverted chrominance signal is used when the drop-out occurs is that the phase of the chrominance signal is inverted or changed by 180.degree. at each successive line (H).
FIG. 2 shows one example of the chroma inverter 110 that may be used in the aforesaid drop-out compensation circuit. Such chroma inverter, as disclosed in U.S. Pat. No. 3,564,123, comprises input and output transformers 111 and 112, with the chrominance signal C being supplied to a terminal 113 of the input transformer 111 and a chrominance signal C', the phase of which is inverted, as required, being developed at a terminal 114 of the output transformer 112.
Between the input and output transformers 111 and 112, there are provided 4 switching diodes D.sub.1 to D.sub.4 connected as shown in FIG. 2. When a command signal applied to a terminal 115 is at "L" (low) level, the diodes D.sub.1 and D.sub.2 are turned on, while the diodes D.sub.3 and D.sub.4 are turned off. When, on the other hand, the command signal is at "H" (high) level, the diodes D.sub.1 and D.sub.2 are turned off, while the diodes D.sub.3 and D.sub.4 are turned on. Consequently, the chrominance signal applied to the input side of the output transformer 112 is made to have an opposite polarity to the preceding polarity so that when the command signal is at "H" level, the phase-inverted chrominance signal C' is developed at the output terminal 114.
With the conventional chroma inverter of FIG. 2, it is only possible to provide the chrominance signal with the phase 0 or .pi. by controlling the polarity of the command signal. Accordingly, although the chroma inverter of the described type can be applied to a dropout compensation circuit for a chrominance signal of NTSC format, it cannot be used for a chrominance signal of PAL format which requires a phase shift of .pi./2. Therefore, the described conventional chroma inverter cannot be universally used and also such construction of the conventional chroma inverter is not suitable for digital signal processing.